1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor device with a self-aligned groove channel formed at edges of source/drain regions therein and a method for manufacturing the same.
2. Description of the Prior Art
FIG. 1 shows a construction of a prior art metal oxide semiconductor (hereinafter, referred to as "MOS") device in which an active layer is formed between two field oxide layers.
As shown in FIG. 1, the prior art MOS device comprises a gate electrode 14 formed on a silicon substrate 10 with a gate insulating layer 12 interposed therebetween, source/drain regions formed between the field oxide layer 18 and the gate electrode 14, and a channel region 11 formed just under the gate insulating layer 12. Reference numeral 20 is an insulating layer for electrically isolating the gate and source/drain electrodes, and reference numeral 22 is source/drain electrode formed on the source/drain region 16 through a contact hole.
In the prior art MOS device of FIG. 1, a length of the channel region 11 must be shortened in proportion to integration thereof, and also a junction depth of the source/drain region 16 must be made shallow in accordance with a scaling rule.
However, if a length of the channel 11 is shortened, a leakage current is increased due to punch-through and the like. To reduce such a leakage current, a junction depth of the source/drain region 16 must be made shallower. If the junction depth thereof is made shallower, resistance is increased in the source/drain region 16. In fabrication of the MOS device having a shallow source/drain region, particularly during performing metallization, a spike-shaped metal such as aluminum or the like is penetrated into the silicon substrate 10. There arises the problem that such an MOS device has seriously lowered reliability due to junction breakdown and electro-migration caused by a spiking of metal.
In addition, the above-mentioned problem is not eliminated even in an MOS device having an LDD (lightly doped drain) structure in which a relatively lightly doped impurity region relative to a source/drain region is formed between the source/drain region and the channel region.
As described above, in the case that an MOS device has a channel having the length of less than a micron, there arise the problems that a short channel effect occurs in the device and resistance is increased in source/drain region therein.